1. Field of the Invention
The present invention generally relates to techniques for testing semiconductor devices, and, more particularly, to techniques for testing integrated circuits that include logic circuitry portions and embedded memory portions with respective scan chains and memory built-in self test logics connected thereto.
2. Description of the Related Art
In manufacturing semiconductor devices including a relatively complex circuitry, the testing of the device may represent a part of the manufacturing process, which is frequently under-estimated in terms of cost and effort required to obtain reliable data with respect to proper functionality and reliability of the device. One reason in failing to meet performance specifications of the integrated circuit may reside in design errors that may be identified and remedied by circuit verification on the basis of software simulation and/or prototype testing prior to mass production of the integrated circuits under consideration. An improper functionality of the integrated circuit may further be caused by the manufacturing process itself when the completed circuitry does not correspond to the verified circuit design owing to process fluctuations in one or more of a large number of process steps. Although measurement and test procedures are incorporated at many points in the manufacturing process, it is nevertheless extremely important to ascertain the correct functioning of the final semiconductor device, since, according to a common rule of thumb, the costs caused by defective chips increase with each assembly phase by approximately one order of magnitude. For example, the costs caused by a defective circuit board including a faulty chip are typically significantly higher than identifying a defective chip prior to shipping and assembling the circuit board. The same holds true for a system, when a failure thereof is caused by one or more defective circuit boards as a downtime of an industrial system may result in averaged costs of approximately several hundred dollars per minute compared to a price of a few dollars for an integrated circuit chip having caused the defect.
Hence, there is a vital interest in developing test procedures to identify as many defects as possible in completed integrated circuits while not unduly increasing the total manufacturing costs. In particular, with the demand for more features and lower costs of circuits, there is a tendency to integrate a plurality of different circuit portions into a single chip to provide a complete system on a chip (SOC). A semiconductor device comprising various functional blocks may typically include, in addition to one or more logic blocks, one or more embedded memory portions, such as are used as on-chip cache for CPUs or as buffers for data packets that are transferred between different clock domains.
As discussed above, economic constraints force semiconductor manufacturers to not only minimize the defect level of the total manufacturing process, but also to provide, in combination with a reduced defect level, a high fault coverage to reduce the delivery of defective chips at reasonable cost for appropriate test procedures and techniques. For moderately complex integrated circuits, it has become standard practice to develop the basic design of the circuit while taking into consideration a plurality of constraints posed by effective test procedures. Moreover, typically additional hardware resources are provided in the chip that may enable the identification of faulty circuit components for a broad class of operating conditions, wherein the additional hardware resources in combination with design specifics of the basic circuit and sophisticated test procedures and test patterns substantially determine the fault coverage of the test procedure.
In many circuit designs, the functional logic portion is tested by so-called scan chains, which represent a chain of flip-flops connected to a specific area of the functional logic in such a way that the functional logic or a specific area thereof may be initialized with a desired state that has previously been entered into the scan chain. Moreover, upon providing one or more clock signals to the functional logic, the state thereof, that is the state of each logic gate connected to a dedicated flip-flop of the scan chain, may then be stored in the scan chain and may be shifted out by supplying respective shift clock signals to the scan chain. Depending on the bit pattern or input vector entered into the scan chain for initializing the functional logic, corresponding faulty logic gates may be identified. However, the fault coverage, i.e., the potential for identifying any error within the functional logic, significantly depends on the design, selection and number of appropriate scan chains and suitable input vectors. In principle, such scan test techniques may also be modified to include the testing of memory portions, wherein, however, only for small memories, appropriate scan test patterns, i.e., the number and size of appropriate input vectors, may exhibit a size that allows the testing of memory portions within acceptable time intervals.
For this reason, frequently a so-called memory built-in self test (MBIST) logic is provided as an additional hardware resource within a chip, to implement a memory test procedure requiring fewer clock cycles and supporting the testing of important extended fault models that are specific to memories. With reference to FIGS. 1a and 1b, the configuration and the test procedures for a representative conventional semiconductor device including functional logic and a memory portion are described in more detail to more clearly illustrate the problems involved.
FIG. 1a schematically shows a circuit diagram of a semiconductor device 100 including a functional logic circuitry 110, which may be connected to a memory portion 120 via write lines, read lines and control lines that are commonly referred to as lines 121. The device 100 further comprises a scan chain 140 connected to the logic circuitry 110, wherein, as previously discussed, the scan chain 140 may include a plurality of flip-flops, which are connected to the logic circuitry 110 such that dedicated logic gates may be initialized by the scan chain and resulting states of the dedicated logic gates, after one or more clock cycles for operating the logic 110, may be stored in and retrieved from the scan chain 140 at an output 141 thereof. The device 100 further comprises an MBIST logic 130 including, for instance, a finite state machine 131 for implementing a desired algorithm for testing the memory portion 120. The MBIST logic 130 further comprises all components required for disconnecting the memory portion 120 from the functional logic 110 to enable the operation of the memory portion 120 fully under control of the MBIST logic 130 when operating the logic 130 for the memory test.
On the other hand, when disabled, the MBIST logic 130 is “transparent” for the lines 121 to allow proper operation of the logic circuitry 110 in combination with the memory portion 120. The MBIST logic 130 comprises a first control input 132, which is also referred to as MBIST-start, and a second control input 133, also indicated in the drawing as MBIST-enable. Moreover, a first output 134, also referred to in the drawing as MBIST-good, and a second output 135, also indicated as MBIST-done, are provided in the MBIST logic 130. It should be noted that, for convenience, any additional inputs or outputs of the logic 130, such as clock inputs, reset inputs and other control lines, are not shown.
When operating the device 100 in a memory test mode, the MBIST logic 130 may be enabled by providing a corresponding signal at the input 133 (MBIST-enable) to disconnect the memory portion 120 from the surrounding logic circuitry 110. By supplying a corresponding signal at the input 132 (MBIST-start), the circuit portion 130 is started to generate address values and to write data into the memory portion 120. The circuit 130 may also include a comparator, which may be configured to check if the data written into the memory 120 may be correctly read back from the memory, and which may provide a corresponding value at the output 134 (MBIST-good). For instance, the value of the output 134 may remain at logic “1” as long as no error occurs in writing data into the memory 120 and reading back the data, while the output 134 may be reset to a logic “0” once an error is detected. After the test of the memory 120 is completed, a corresponding signal may be presented at the output 135 (MBIST-done), for instance, the output 135 may be switched from logic “0” to logic “1” if the test is completed.
As previously explained, incorporating the MBIST logic 130 provides more efficient testing of the memory 120, as would be obtained by testing the device 100 by modifying the scan chain 140 and the required scan patterns. After a successful memory test, the logic 110 may then be tested by initializing the logic 110 with a respective input vector applied to the scan chain 140 via the input 142, operating the logic 110, that is, scanning the logic 110 by supplying respective scan clock signals to the logic 110, and reading out the state of the scan chain after a predefined number of scan clock signals by correspondingly shifting out the states of the scan flip-flops while the operation of the logic 110, i.e., the scan clock signals, is interrupted. On the basis of the output vector sequentially obtained at the output 141, the functionality of logic 110 may be verified to a degree determined by the scan test algorithm and the configuration of the scan chain 140. Due to the configuration of the device 100, the scan test and the memory test have to be sequentially performed, thereby requiring a moderately high amount of test time. Furthermore, the scan test of the device 100 is not independent from the memory test, since, without having intensively verified the proper functionality of the memory 120, any fault detected by the scan test may not unambiguously be assigned to a faulty component in the logic circuitry 110. Moreover, the circuit portion 131 controlling the MBIST logic 130 and preferably all other flip-flops of the MBIST logic 130 may be included into the scan chain 140 to ensure the correct function of the logic 130 during the memory test. However, merely providing additional scan flip-flops for the MBIST logic 130 and incorporating these additional scan flip-flops into the scan chain 140 may significantly complicate the situation during testing of the device 100, as the scan test and the memory test mutually depend on each other. Therefore, it may be advantageous to add additional circuitry to form a bypass for the memory portion 120 during scanning of the logic 110 and the MBIST logic 130.
FIG. 1b schematically shows a circuit diagram illustrating, in principle, the semiconductor device 100 with a bypass logic 150 that offers an enhanced flexibility in performing scan tests and memory tests. The bypass logic 150 may provide a function that maps values of address, write and control lines to the values of the read lines of the memory portion 120. Advantageously, the implemented function supports fault propagation and allows the generation of all possible output values so that any logic components between the inputs and outputs of the memory portion 120 as well as the adjacent scan flip-flops can be readily tested. In other approaches, it has been suggested to emulate or surround the memory by scanable registers to provide more flexibility in scanning the logic 110 and testing the memory portion 120.
During the scan test, the MBIST logic 130 has to be disabled so that the MBIST logic 130 is “transparent,” while the bypass logic 150 provides the correct functionality of the logic 110, thereby not requiring the operation of the memory portion 120. Thus, any faulty memory cells will not affect the result of the scan test. On the other hand, while a memory test is running, i.e., while the MBIST logic 130 is active, a scan test must be disabled to render the bypass logic 150 “transparent” to allow for an undisturbed test procedure of the memory cells in the memory portion 120.
Consequently, although the approaches described with reference to FIG. 1b provide an enhanced flexibility in performing scan tests and memory tests compared to the basic circuit design shown in FIG. 1a, there is still a significant effort to be made in performing reliable test procedures, as the scan test runs have to be carried out separately to the memory test runs. Moreover, the conventional technique as described with reference to FIGS. 1a and 1b may not be very efficient during stress tests in which a high switching activity is required in the combinatorial logic, i.e., the logic circuitry portion 110, while test data are written into and read out from the memory to verify a correct function of the memory during specified stress conditions.
In view of the problems identified above, there is a need for an improved technique that provides more efficient testing of semiconductor devices while maintaining the additional hardware and software overhead required for performing test procedures at a low level.